Title :
A system for automated built-in self-test of embedded memory cores in system-on-chip
Author :
Garimella, Srinivas ; Stroud, Charles
Author_Institution :
Dept. of Electr. & Comput. Eng.,, Auburn Univ., AL, USA
Abstract :
A system for automatic generation of built-in self-test (BIST) for embedded memory cores in a system-on-chip (SoC) is presented. The BIST approach tests RAMs of any address and data bus widths and can test both single-port and dual-port RAMs operating in synchronous or asynchronous mode. A field programmable gate array (FPGA) independent BIST model is developed using VHDL. The parameterized VHDL model has been synthesized and used to test various sizes and types of embedded RAMs in SoCs and FPGAs.
Keywords :
automatic testing; built-in self test; embedded systems; field programmable gate arrays; hardware description languages; random-access storage; system-on-chip; RAM; VHDL; automated built-in self-test; embedded memory cores; field programmable gate arrays; system-on-chip; Automatic testing; Built-in self-test; Circuit testing; Field programmable gate arrays; Hardware design languages; Programmable logic arrays; Random access memory; Read-write memory; System testing; System-on-a-chip;
Conference_Titel :
System Theory, 2005. SSST '05. Proceedings of the Thirty-Seventh Southeastern Symposium on
Print_ISBN :
0-7803-8808-9
DOI :
10.1109/SSST.2005.1460876
