Low Vt Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases

This paper reports a novel approach to implement low V_t Ni-FUSI bulk CMOS by using a dysprosium oxide (DyO) cap layer on both HfSiON and SiON host dielectrics. We show for the first time that an ultra-thin DyO cap layer (5 Aring) can lower the NiSi FUSI nFET V_t by 300 mV/500 mV on HfSiON/SiON (resulting in a V_t,lin of 0.25 V/0.18 V respectively), w/o compromising the T_inv (<1 Aring variation), gate leakage, mobility or reliability. We observed that the DyO cap on SiON can convert into a DySiON silicate with similar electrical properties as HfSiON but much lower Vt, greatly-improved PBTI and 150times lower J_g wrt SiON. By demonstrating a novel DyO cap layer selective removal process, this work also points out the feasibility to realize low V_t CMOS using either dual phase (NiSi, Ni₃₂Si₁₂) or single phase (Ni₂Si) FUSI gate for both n-and pFETs.