• DocumentCode
    3485211
  • Title

    Impact of Mobility Boosters (XsSOI, CESL, TiN gate) on the Performance of ≪100≫ or ≪110≫ oriented FDSOI cMOSFETs for the 32nm Node

  • Author

    Andrieu, Francois ; Faynot, O. ; Rochette, F. ; Barbé, J.C. ; Buj, C. ; Bogumilowicz, Y. ; Allain, F. ; Delaye, V. ; Lafond, D. ; Aussenac, F. ; Feruglio, S. ; Eymery, J. ; Akatsu, T. ; Maury, P. ; Brévard, L. ; Tosti, L. ; Dansas, H. ; Rouchouze, E. ; Ha

  • Author_Institution
    CEA LETI-MINATEC, Grenoble
  • fYear
    2007
  • fDate
    12-14 June 2007
  • Firstpage
    50
  • Lastpage
    51
  • Abstract
    For the first time, we integrated 1.9 GPa eXtra-strained silicon on insulator (XsSOI) substrates in FDSOI n and pMOSFETs with gate length (LG) and width (W) down to 25 nm. Due to the high stress levels, significant ION-IOFF improvements were obtained not only for nMOS but also for pMOS. We compared those results with the performance of devices strained by contact etch stop layer (CESL), for different device orientations (<110> or <100>) and feature sizes (LG, W). We demonstrate that, similarly to XsSOI, a single tensile CESL can improve both n and pMOS performance, leading to ION,n=700 muA/mum and ION,p=430 muA/mum at IOFF=140 pA/mum, this for LG<35 nm, W=50 nm and VDD=1 V along the <100> direction.
  • Keywords
    MOSFET; nanoelectronics; silicon-on-insulator; substrates; <100> substrates orientation; <110> substrates orientation; FDSOI cMOSFET; Si; TiN; contact etch stop layer; device orientations; extra-strained silicon on insulator substrates; mobility boosters; pressure 1.9 GPa; size 32 nm; CMOSFETs; Paper technology; Tin; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, 2007 IEEE Symposium on
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-4-900784-03-1
  • Type

    conf

  • DOI
    10.1109/VLSIT.2007.4339723
  • Filename
    4339723