0.7 V SRAM Technology with Stress-Enhanced Dopant Segregated Schottky (DSS) Source/Drain Transistors for 32 nm Node

Author

Onoda, H. ; Miyashita, K. ; Nakayama, T. ; Kinoshita, T. ; Nishimura, H. ; Azuma, A. ; Yamada, S. ; Matsuoka, F.

Author_Institution

Toshiba Corp., Tokyo

fYear

2007

fDate

12-14 June 2007

Firstpage

76

Lastpage

77

Abstract

For the fist time, low supply voltage SRAM operation with stress-enhanced dopant segregated Schottky (DSS) source/drain transistors is demonstrated. At constant SRAM cell current of 40 muA, we achieve two orders of magnitude lower bit-line leakage than conventional technologies at V_dd=0.7 V, while in case of constant bit-line leakage of 10 nA, supply voltage is successfully reduced down by 0.1 V. DSS technology is promising for low voltage SRAM operation for 32 nm node and beyond.

Keywords

SRAM chips; Schottky gate field effect transistors; SRAM technology; constant bit-line leakage; current 40 muA; size 32 nm; stress-enhanced dopant segregated Schottky source/drain transistors; voltage 0.7 V; Decision support systems; FETs; Large scale integration; Low voltage; Manufacturing processes; Random access memory; Research and development; Semiconductor device manufacture; Stability; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-03-1

Type

conf

DOI

10.1109/VLSIT.2007.4339733

Filename

4339733