DocumentCode
3485565
Title
Toward Variability-Aware Design
Author
Onodera, Hidetoshi
Author_Institution
Kyoto Univ., Kyoto
fYear
2007
fDate
12-14 June 2007
Firstpage
92
Lastpage
93
Abstract
Measured variabilities from 0.35 mum to 90 nm processes are explained with a growing concern of within-die components. Variability impact on circuit performance is examined. Design techniques" for mitigating the variability are discussed that include the introduction of regularity and "variation-aware reconfiguration of FPGA.
Keywords
field programmable gate arrays; integrated circuit design; FPGA; IC design; circuit performance; size 0.35 mum to 90 nm; variability-aware design; variation-aware reconfiguration; within-die components; Circuit optimization; Current measurement; Delay; Driver circuits; Field programmable gate arrays; Fluctuations; Informatics; Integrated circuit interconnections; Semiconductor device measurement; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 2007 IEEE Symposium on
Conference_Location
Kyoto
Print_ISBN
978-4-900784-03-1
Type
conf
DOI
10.1109/VLSIT.2007.4339740
Filename
4339740
Link To Document