Author :
Yang, B. Frank ; Nummy, K. ; Waite, A. ; Black, L. ; Gossmann, H. ; Yin, H. ; Liu, Y. ; Kim, B. ; Narasimha, S. ; Fisher, P. ; Meer, H.V. ; Johnson, J. ; Chidambarrao, D. ; Kim, S.D. ; Sheraw, C. ; Wehella-gamage, D. ; Holt, J. ; Chen, X. ; Park, D. ; Sun
Abstract :
This work demonstrates that the ~2times mobility advantage of (110) PMOS over (100) PMOS is maintained down to 190 nm liners poly-pitch for devices under compressive stress. (110) PMOS with 3.5 GPa compressively stressed liners demonstrate strong channel drives with Ion=800 muA/mum at Ioff=100 nA/mum (Vdd=10 V) for 190 nm poly-pitch, the highest reported to date for 45-nm-node (110) PMOS using conventional gate dielectrics without eSiGe stressors. Additionally, (110) PMOS show better scalability, with 15% smaller total Ion degradation than (100) PMOS when poly-pitch scales from 250 nm to 190 nm.
Keywords :
MOS integrated circuits; dielectric materials; driver circuits; PMOS drive current; compressively stressed liners; gate dielectrics; mobility advantage; poly-pitch scaling characteristics; stress dependence; CMOS process; Compressive stress; Degradation; Dielectric devices; Dielectric substrates; Fabrication; Leakage current; MOS devices; Scalability; Silicon;
