Exploiting hysteresis in a CMOS buffer

Author

Secareanu, Radu M. ; Adler, Victor ; Friedman, Eby G.

Author_Institution

Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA

Volume

1

fYear

1999

fDate

1999

Firstpage

205

Abstract

A high drive CMOS buffer circuit characterized by a voltage transfer characteristic (VTC) with low threshold voltages and hysteresis is proposed. The proposed circuit is capable of restoring slow transition times and distorted input signals with a minimum delay penalty. Due to the hysteresis characteristic of this buffer, a comparison with a Schmitt-trigger is provided. An important application of this circuit is the restoration of slow transitioning signals propagated along an RC interconnect. The circuit can be used in conjunction with existing repeater insertion methodologies to decrease the delay of an RC line

Keywords

CMOS digital integrated circuits; buffer circuits; delays; hysteresis; RC interconnect; RC line delay reduction; Schmitt-trigger comparison; high drive CMOS buffer circuit; hysteresis characteristic; low threshold voltages; minimum delay penalty; slow transitioning signals restoration; voltage transfer characteristic; Art; Circuit simulation; Hysteresis; IEL; Milling; Propagation delay; Signal restoration; Switches; Tail; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on

Conference_Location

Pafos

Print_ISBN

0-7803-5682-9

Type

conf

DOI

10.1109/ICECS.1999.812259

Filename

812259