DocumentCode :
348597
Title :
Minimising communications of synchronous hardware
Author :
De Melo, Ana C V
Author_Institution :
Dept. of Comput. Sci., Sao Paulo Univ., Brazil
Volume :
1
fYear :
1999
fDate :
1999
Firstpage :
271
Abstract :
The cost on the development of computational systems grows with their complexity. So, the interest of producing elements as minimal as possible arises. Due to the current growing interest in designing hardware as concurrent systems, techniques to minimise interacting processes arbitrarily connected are highly desired. The existing techniques for minimising interacting processes have only addressed minimisation in the number of states. Here we present a technique for minimising interacting processes in the number of communication ports
Keywords :
communication complexity; concurrency theory; formal verification; minimisation; process algebra; ELLA process algebra; bisimulation; communication minimisation; communication ports; computational complexity; concurrent systems; formal verification; interacting process minimisation; synchronous hardware; Algebra; Computer science; Controllability; Costs; Hardware;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
Type :
conf
DOI :
10.1109/ICECS.1999.812275
Filename :
812275
Link To Document :
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