Improved Cell Performance for sub-50 nm DRAM with Manufacturable Bulk FinFET Structure

FinFET, the milestone for sub-50 nm DRAM cell transistor has been successfully demonstrated by a unique fabricating method with novel concept. We obtained a core solution of front-end-of-line process and structure, focusing on short channel behavior, off-state leakage, and saturation current. We have developed the scheme that is able to suppress off-state leakage current below 1 fA/cell with p⁺ poly-Si gate. We have also examined mobility and parasitic engineering techniques to maximize the cell performance (DeltaIon > 48 %). In conclusion, we propose the effective guideline for highly manufacturable FinFET for DRAM application at the sub-50 nm node.