Redesigning Product Workflow for Excellence

Customers demand more and more integrated functions on one chip; as a result, semiconductor product complexity is increasing tremendously. This development results in increasing production process complexity, reflected in the incorporation of additional lithography layers, for example, which causes longer cycle times, higher costs and extended feedback loops for making quality improvement. Each additional process step introduces at least five additional logistics steps, as each lot has to be handled and transported twice over and also stored temporarily. This scenario is leading to a `logistical trap´ in which there is a high proportion of non value-add time. The main leverage to improve long cycle times is the redesign of product workflow for excellence, which means aiming for short cycle times, low production costs and, at the same time, high product quality.