1-bit and multi-bit envelope delta-sigma modulators for CDMA polar transmitters

The 1-bit second-order EDSM with OSR 32 for a CDMA polar transmitter has been designed using Cadence circuit simulation, where the design specifications have been extracted from the Agilent ADS Ptolemy simulation. And multi-bit EDSM is able to reduce the sampling frequency, while providing reduced slew limitation and reduced switching power consumption. This paper proposes one possible architecture with multi-bit EDSM named the decoded switch control method. Multi-level power driving is expected to provide higher linearity and higher efficiency.