Optimization of the NMOS and PMOS gate cross-connected rectifier for RF power extraction in RFID applications

The NMOS and PMOS gate cross-connected bridge rectifier has been proved an efficient way to realize the power extraction for passive RFID applications. In this paper, such a rectifier has been analyzed from its different state during the period of the RF input signal. The calculations reveal the essence of this circuit and some useful relations are calculated and plotted by MATLAB. With these relations this circuit can be easily optimized. It agrees very well with the results simulated by a circuit simulator such as Cadence but the optimization and design time-consumption is greatly reduced. For much higher output voltage the multi-stages structure may be applied to keep the basic rectifiers of each stage in their most efficient operation point.