Title :
Area-I/O flip-chip routing for chip-package co-design
Author :
Fang, Jia-Wei ; Chang, Yao-Wen
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
Abstract :
The area-I/O flip-chip package provides a high chip-density solution to the demand of more I/Opsilas in VLSI designs; it can achieve smaller package size, shorter wirelength, and better signal and power integrity. In this paper, we introduce the routing problem for chip and package co-design and present the first work in the literature to handle the multiple Re-Distribution Layer (RDL) routing problem for flip-chip designs, considering pin and layer assignment, total wirelength minimization, and chip-package co-design. Our router adopts a two-stage technique of global routing followed by RDL routing. The global routing assigns each block port to a unique bump pad via an I/O pad and decides the RDL routing among I/O pads and bump pads. Based on the minimum-cost maximum-flow algorithm, we can guarantee 100% RDL routing completion after the assignment and the optimal solution with the minimum wirelength. The RDL routing efficiently distributes the routing points between two adjacent bump pads and then generates a 100% routable sequence to complete the routing. Experimental results based on 10 industry designs demonstrate that our router can achieve 100% routability and the optimal routing wirelength under reasonable CPU times, while related works cannot.
Keywords :
VLSI; chip scale packaging; flip-chip devices; input-output programs; VLSI designs; area-I/O flip-chip routing; bump pads; chip-package codesign; minimum-cost maximum-flow algorithm; multiple redistribution layer routing problem; routing wirelength; Design engineering; Electronics packaging; Inductance; Joining processes; Large-scale systems; Routing; Signal design; Very large scale integration;
Conference_Titel :
Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2819-9
Electronic_ISBN :
1092-3152
DOI :
10.1109/ICCAD.2008.4681624