DocumentCode
3488050
Title
Multigrid on GPU: Tackling Power Grid Analysis on parallel SIMT platforms
Author
Feng, Zhuo ; Li, Peng
Author_Institution
Dept. of Electr. & Comput. Eng., Texas A&M Univ., College Station, TX
fYear
2008
fDate
10-13 Nov. 2008
Firstpage
647
Lastpage
654
Abstract
The challenging task of analyzing on-chip power (ground) distribution networks with multi-million node complexity and beyond is key to todaypsilas large chip designs. For the first time, we show how to exploit recent massively parallel single-instruction multiple-thread (SIMT) based graphics processing unit (GPU) platforms to tackle power grid analysis with promising performance. Several key enablers including GPU-specific algorithm design, circuit topology transformation, workload partitioning, performance tuning are embodied in our GPU-accelerated hybrid multigrid algorithm, GpuHMD, and its implementation. In particular, a proper interplay between algorithm design and SIMT architecture consideration is shown to be essential to achieve good runtime performance. Different from the standard CPU based CAD development, care must be taken to balance between computing and memory access, reduce random memory access patterns and simplify flow control to achieve efficiency on the GPU platform. Extensive experiments on industrial and synthetic benchmarks have shown that the proposed GpuHMD engine can achieve 100times runtime speedup over a state-of-the-art direct solver and be more than 15times faster than the CPU based multigrid implementation. The DC analysis of a 1.6 million-node industrial power grid benchmark can be accurately solved in three seconds with less than 50 MB memory on a commodity GPU. It is observed that the proposed approach scales favorably with the circuit complexity, at a rate about one second per million nodes.
Keywords
differential equations; distribution networks; network topology; power grids; CPU based multigrid implementation; GPU-accelerated hybrid multigrid algorithm; GPU-specinc algorithm design; circuit topology transformation; multimillion node complexity; on-chip power distribution networks; performance tuning; random memory access patterns; single-instruction multiple-thread based graphics processing unit platforms; workload partitioning; Algorithm design and analysis; Central Processing Unit; Chip scale packaging; Circuit topology; Graphics; Network-on-a-chip; Partitioning algorithms; Performance analysis; Power grids; Runtime;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on
Conference_Location
San Jose, CA
ISSN
1092-3152
Print_ISBN
978-1-4244-2819-9
Electronic_ISBN
1092-3152
Type
conf
DOI
10.1109/ICCAD.2008.4681645
Filename
4681645
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