DocumentCode :
3489013
Title :
Improved sub-threshold slope in RF vertical MOSFETS using a frame gate architecture
Author :
Hakim, M.M.A. ; Uchino, T. ; R-White, W. ; Ashburn, P. ; Tan, L. ; Buiu, O. ; Hall, S.
Author_Institution :
Univ. of Southampton, Southampton
fYear :
2008
fDate :
15-19 Sept. 2008
Firstpage :
95
Lastpage :
98
Abstract :
We report a CMOS-compatible vertical MOSFET, which incorporates a frame gate architecture suitable for application in RF circuits. Fabricated surround gate vertical MOSFETs with the frame gate architecture show no degradation of short channel effects when the channel length is scaled, while control devices show significantly degraded sub-threshold slope and DIBL. The frame gate vertical MOSFETs show near ideal sub-threshold slopes of 70-80 mV/decade and DIBL of 30-35 mV/V in a 100 nm gate length nMOS device. In contrast, the control vertical MOSFETs without the frame gate exhibit sub-threshold slopes of 110 to 140 mV/decade and DIBL of 100 to 280 mV/V. This improved sub-threshold slope is explained by the elimination of etch damage during gate etch.
Keywords :
CMOS integrated circuits; MOSFET; boron; elemental semiconductors; etching; radiofrequency integrated circuits; silicon; CMOS-compatible vertical MOSFET; RF circuits; Si:B; channel length; frame gate architecture; gate etching; gate length; short channel effects; size 100 nm; subthreshold slopes; CMOS technology; Capacitance; Circuits; Degradation; Dry etching; Immune system; MOSFETs; Optical microscopy; Oxidation; Radio frequency;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European
Conference_Location :
Edinburgh
ISSN :
1930-8876
Print_ISBN :
978-1-4244-2363-7
Electronic_ISBN :
1930-8876
Type :
conf
DOI :
10.1109/ESSDERC.2008.4681707
Filename :
4681707
Link To Document :
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