Silicon on thin BOX (SOTB) CMOS for ultralow standby power with forward-biasing performance booster

Author

Ishigaki, T. ; Tsuchiya, R. ; Morita, Y. ; Yoshimoto, H. ; Sugii, N. ; Iwamatsu, T. ; Oda, H. ; Inoue, Y. ; Ohtou, T. ; Hiramoto, T. ; Kimura, S.

Author_Institution

Central Res. Lab., Hitachi, Ltd., Kokubunji

fYear

2008

fDate

15-19 Sept. 2008

Firstpage

198

Lastpage

201

Abstract

Ultralow off-current (I_off les 1 pA/mum) ldquosilicon on thin BOX (SOTB)rdquo CMOSFETs were fabricated in 65-nm technology. Gate-induced drain leakage (GIDL) was adequately reduced by controlling the gate-overlap length with an additional offset spacer. Small threshold-voltage (V_th) variation under a wide-range back-gate-bias (V_bg) condition and suppressed I_off variation by V_bg control were demonstrated. Faster inverter delay (tau_pd) than conventional low-standby-power (LSTP) bulk CMOS was also achieved.

Keywords

CMOS integrated circuits; MOSFET; elemental semiconductors; silicon; CMOS; MOSFET; Si; forward-biasing performance booster; gate-induced drain leakage; gate-overlap length; inverter delay; silicon on thin BOX; size 65 nm; ultralow standby power; ultrathin buried oxide; wide-range back-gate-bias condition; CMOS technology; CMOSFETs; Delay; Fabrication; Inverters; Laboratories; MOSFET circuits; Silicon; Space technology; Textile industry;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European

Conference_Location

Edinburgh

ISSN

1930-8876

Print_ISBN

978-1-4244-2363-7

Electronic_ISBN

1930-8876

Type

conf

DOI

10.1109/ESSDERC.2008.4681732

Filename

4681732