A 0.17–1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme

A wide-range low-jitter digital DLL using 0.18 um single-poly four-metal CMOS technology is proposed that uses an open-loop time-to-digital converter (TDC)-based DCC circuit with 10 cycles of maximum locking time by virtue of pulse width detection scheme. In addition, the DLL uses a semi dual delay line to remove the boundary switching problem and to optimize its area and power consumption. Thus, the proposed DLL operates over a frequency range from 170 MHz to 1.4 GHz. The peak-to-peak jitter is 13.8 ps at 1.4 GHz and the power consumption is reduced to 27 mW.