Associative search based test algorithms for test acceleration in FAST-RAMs

To accelerate deterministic functional memory chip testing, the authors propose modifying a memory chip using circuit structures known from flag-oriented associative memories. Based on these modifications new test algorithms have been developed. Compared with existing test algorithms the complexity of algorithms developed for fault detection is one or two orders lower. For fault localization it is approximately one order lower and depends additionally on the number of faulty cells in a memory chip. It is shown that this complexity can be reduced further using contents-oriented processing of the information stored in a memory with corresponding circuit structures. In this contribution the basics of the new test approach, the structure of the newly developed test algorithms, the hardware requirements and the achievable test acceleration are discussed