• DocumentCode
    349074
  • Title

    A new compact programmable νBJT cellular neural network structure with adjustable neighborhood layers for image processing

  • Author

    Yen, Wen-Cheng ; Wu, Chung-Yu

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • Volume
    2
  • fYear
    1999
  • fDate
    5-8 Sep 1999
  • Firstpage
    713
  • Abstract
    A new compact structure called the neuron-bipolar cellular neural network (νBJT) CNN is proposed and analyzed. In the new structure, the νBJT and lambda BJT realized by parasitic pnp BJTs in the CMOS process are used to implement the neuron whereas the coupling MOS resistor is used to realize the symmetric synapse weights among various neurons. It has the advantages of compact structure and small chip size. In order to further realize the asymmetric template coefficients with negative values, the coupling MOS resistor is replaced by a fully programmable stage containing two lateral PNP bipolar junction transistors and two MOS switches. The proposed symmetric νBJT CNN and fully programmable νBJT CNN with single neighborhood layer r=1 have been successfully applied to noise removal, hole filling, connected component detection, and shadowing creation. Moreover, the proposed νBJT CNN can be easily extended to realize the multi-layer neighborhood structure. Thus the proposed νBJT CNN has great potential in the VLSI implementation of neural networks. A test chip consisting of 16×16 νBJT CNN has been designed in 0.6 μm CMOS technology
  • Keywords
    BiCMOS integrated circuits; VLSI; cellular neural nets; image processing equipment; image texture; neural chips; programmable circuits; 0.6 micron; CMOS technology; VLSI implementation; adjustable neighborhood layers; asymmetric template coefficients; chip size; connected component detection; coupling MOS resistor; fully programmable stage; hole filling; image processing; multi-layer neighborhood structure; parasitic pnp BJTs; programmable νBJT cellular neural network structure; shadowing creation; single neighborhood layer; symmetric synapse weights; CMOS process; CMOS technology; Cellular neural networks; Filling; MOSFETs; Neurons; Resistors; Shadow mapping; Switches; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
  • Conference_Location
    Pafos
  • Print_ISBN
    0-7803-5682-9
  • Type

    conf

  • DOI
    10.1109/ICECS.1999.813208
  • Filename
    813208