Efficient VLSI implementation of modern symmetric block ciphers

Author

Schubert, A. ; Anheier, W.

Author_Institution

Inst. fur Theor. Elektrotech. und Microelektron., Bremen Univ., Germany

Volume

2

fYear

1999

fDate

5-8 Sep 1999

Firstpage

757

Abstract

In this paper efficient VLSI architectures for three modern symmetric block ciphers RC5-32/12/16, SAFER K-128 and 3WAY are discussed. The connection between algorithm properties and VLSI architectures are described. An exemplary performance analysis and comparison of VLSI architectures for a 0.7 μm CMOS standard cell process are carried out. The results of the work are reusable soft and firm cores, which can be embedded in integrated systems and allow high speed data encryption. One of the developed VLSI architectures for the 3WAY algorithm achieves a data throughput up to 1.6 Gbit/s, which is up to now the highest encryption speed of a sym. block cipher realized in a CMOS process

Keywords

CMOS digital integrated circuits; VLSI; computer architecture; cryptography; hardware description languages; 0.7 mum; 1.6 Gbit/s; 3WAY; CMOS standard cell process; RC5-32/12/16; SAFER K-128; VLSI architecture; VLSI implementation; embedded systems; encryption speed; high speed data encryption; performance analysis; symmetric block ciphers; Application software; CMOS process; Cryptography; Data flow computing; Data security; Delay effects; Information security; Performance analysis; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on

Conference_Location

Pafos

Print_ISBN

0-7803-5682-9

Type

conf

DOI

10.1109/ICECS.1999.813219

Filename

813219