Title :
Multi-Bank Register File for Increased Performance of Highly-Parallel Processors
Author :
Johguchi, Koh ; Aoyama, Kenichi ; Sueyoshi, Tetsuya ; Mattausch, Hans Jurgen ; Koide, Tetsushi ; Maeda, Moto ; Hironaka, Tetsuo ; Tanigawa, Kazuya
Author_Institution :
Res. Center for Nanodevices & Syst., Hiroshima Univ.
Abstract :
A multi-bank register file architecture for increasing the register-access clock frequency by up to 95 % and an access arbitration method for avoiding degradation of the cycle number based processor performance are reported. A 4-bank test design in 200 nm gate-length CMOS with 12 ports and 128 registers has 0.39 mm2 area and operates at up to 417 MHz
Keywords :
CMOS integrated circuits; microprocessor chips; parallel architectures; shift registers; 4-bank test design; CMOS process; access arbitration method; cycle number based processor performance; highly-parallel processors; multibank register file architecture; register-access clock frequency; Clocks; Decoding; Degradation; Frequency; Out of order; Parallel processing; Processor scheduling; Random access memory; Registers; Testing;
Conference_Titel :
Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European
Conference_Location :
Montreux
Print_ISBN :
1-4244-0303-0
DOI :
10.1109/ESSCIR.2006.307554
