Title :
A Low-power BitStream Controller for H.264/AVC Baseline Decoding
Author :
Xu, Ke ; Choy, Chiu-Sing ; Chan, Cheong-Fat ; Pun, Kong-Pong
Author_Institution :
Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin
Abstract :
In this paper, the authors present the design and VLSI implementation of a low-power bitstream controller for H.264/AVC baseline profile decoding. It is comprised of bitstream parsing and three dedicated decoders for intra-prediction mode, inter-motion vector and boundary strength. Various low-power design techniques, such as statistic-based data driven decoding, hierarchical FSM decomposition, nonuniform LUT partition favoring smaller tables, module-wise clock gating are employed. Due to a clever architecture design, the proposed work is capable of decoding realtime QCIF of 30 fps at a required operating frequency as low as 1MHz or even slower. A prototype chip, fabricated in a 0.18mum CMOS process, has an area of 3.6mm2 with 47k gate counts and dissipates 113muW of power on a 1.8V supply
Keywords :
CMOS integrated circuits; VLSI; controllers; finite state machines; low-power electronics; program compilers; table lookup; video coding; 0.18 micron; 1.8 V; 113 muW; 30 ft/s; CMOS process; FSM decomposition; H.264/AVC baseline decoding; VLSI implementation; bitstream parsing; data driven decoding; decoders; inter-motion vector; intra-prediction mode; low-power bitstream controller; low-power design techniques; module-wise clock gating; nonuniform LUT partition; Automatic voltage control; Clocks; Decoding; Design engineering; Energy consumption; Frequency; Read-write memory; Table lookup; Very large scale integration; Video coding;
Conference_Titel :
Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European
Conference_Location :
Montreux
Print_ISBN :
1-4244-0303-0
DOI :
10.1109/ESSCIR.2006.307556
