Title :
A robust 1.5Gb/s + 3Gb/s serial PHY with feed-forward correction clock and data recovery
Author :
Redman-White, W. ; Bugbee, M. ; Dobbs, S. ; Wu, X. ; Balmford, R. ; Nuttgens, J. ; Kiani, U. ; Clegg, R. ; den Besten, G.W.
Author_Institution :
NXP Semicond., Southampton
Abstract :
This paper describes a 1.5 Gb/s and 3 Gb/s serial PHY architecture aimed at robust operation and ease of porting to smaller technologies. A minimum of precision analogue functions are used, and all digital functions use rail-to-rail CMOS. A single fixed low-jitter PLL serves the transmit and receive paths in both modes, and a new oversampling CDR relaxes the requirements for the analogue front-end as well as for the signal quality. The design occupies <0.4 mm2 in 90 nm CMOS and consumes 75 mW.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; clock and data recovery circuits; feedforward; low-power electronics; phase locked loops; system-on-chip; SoC; analogue front-end; analogue-to-digital conversion channels; bit rate 1.5 Gbit/s; bit rate 3 Gbit/s; digital functions; feed-forward correction clock and data recovery; low-jitter PLL; oversampling CDR; precision analogue functions; rail-to-rail CMOS design; serial PHY architecture; size 90 nm; system-on-chip; Bandwidth; CMOS technology; Clocks; Feedforward systems; Frequency; Jitter; Paper technology; Phase locked loops; Physical layer; Robustness;
Conference_Titel :
Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European
Conference_Location :
Edinburgh
Print_ISBN :
978-1-4244-2361-3
Electronic_ISBN :
1930-8833
DOI :
10.1109/ESSCIRC.2008.4681819
