A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS

Author

Anders, Mark ; Kaul, Himanshu ; Hansson, Martin ; Krishnamurthy, Ram ; Borkar, Shekhar

Author_Institution

Circuit Res. Lab., Intel Corporationm Hillsboro, Hillsboro, OR

fYear

2008

fDate

15-19 Sept. 2008

Firstpage

182

Lastpage

185

Abstract

An on-die multi-core circuit-switched network for tera-scale computing, achieving 2.9 Tb/s throughput for random data transmissions on a 64 core 2D mesh and consuming 8 W in 45 nm CMOS at 1.0V, 50degC is described. Use of pipelined circuit-switched transmission, coupled with circuit path queue circuits and packet-switched request circuits enable power consumption of 125 mW/router and efficiency of 363 Gb/s/W, with scalable traffic-dependent throughput up to 6.2 Tb/s.

Keywords

CMOS integrated circuits; network-on-chip; 64 core 2D mesh; 64-core circuit-switched network-on-chip; CMOS integrated circuits; bit rate 2.9 Tbit/s; circuit path queue circuits; on-die multicore circuit-switched network; packet-switched request circuits; pipelined circuit-switched transmission; power 8 W; random data transmissions; size 45 nm; tera-scale computing; voltage 1 V; Channel allocation; Computer networks; Data communication; Energy consumption; Integrated circuit interconnections; Intelligent networks; Network-on-a-chip; Routing; Throughput; Traffic control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European

Conference_Location

Edinburgh

ISSN

1930-8833

Print_ISBN

978-1-4244-2361-3

Electronic_ISBN

1930-8833

Type

conf

DOI

10.1109/ESSCIRC.2008.4681822

Filename

4681822