Program circuit for a phase change memory array with 2 MB/s write throughput for embedded applications

Author

De Sandre, G. ; Bettini, L. ; Calvetti, E. ; Giacomi, G. ; Pasotti, M. ; Borghi, M. ; Zuliani, P. ; Annunziata, R. ; Tortorelli, I. ; Pellizzer, F. ; Bez, R.

Author_Institution

Front End Technol. & Manuf., STMicroelectronics, Agrate Brianza

fYear

2008

fDate

15-19 Sept. 2008

Firstpage

198

Lastpage

201

Abstract

A flexible program circuit for chalcogenide non-volatile memories was developed within a 4Mb ePCM (embedded phase change memory) implemented in 90 nm CMOS technology. The proposed architecture ensures adaptability with respect to process variations and is fully compatible with a single pulse approach or a multiple pulse algorithm for multi-level operation. In the former a write throughput of 2 MB/s is achieved.

Keywords

CMOS memory circuits; embedded systems; phase change memories; CMOS technology; bit rate 2 Mbit/s; chalcogenide nonvolatile memories; embedded applications; embedded phase change memory; flexible program circuit; phase change memory array; process variations; size 90 nm; write throughput; CMOS memory circuits; CMOS technology; Crystalline materials; Flash memory; Flexible printed circuits; Nonvolatile memory; Phase change materials; Phase change memory; Phased arrays; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European

Conference_Location

Edinburgh

ISSN

1930-8833

Print_ISBN

978-1-4244-2361-3

Electronic_ISBN

1930-8833

Type

conf

DOI

10.1109/ESSCIRC.2008.4681826

Filename

4681826