DocumentCode :
3491042
Title :
Parallel switch level fault simulation algorithm/complexity verification using compiled code VHDL
Author :
Ryan, Christopher A. ; Tront, Joseph G.
Author_Institution :
Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
fYear :
1993
fDate :
28-30 Jun 1993
Firstpage :
100
Lastpage :
105
Abstract :
Switch level faults, as opposed to traditional gate level faults, can more accurately model the physical faults found in integrated circuits. Existing fault simulation techniques have a worst-case computational complexity of O(n**2), where n is the number of devices in the circuit. A parallel hardware accelerated fault simulator (PHAFS) has been proposed in order to reduce the complexity to O(L**2), where L is the number of levels of switches encountered when traversing from output to input. The paper presents the algorithm/complexity verification as needed for the prototyping of PHAFS. The verification includes a compiled code VHDL switch level fault simulator
Keywords :
CMOS integrated circuits; circuit analysis computing; computational complexity; digital integrated circuits; integrated circuit testing; parallel programming; specification languages; PHAFS; compiled code VHDL; computational complexity; fault simulation techniques; gate level faults; integrated circuits; parallel hardware accelerated fault simulator; switch level fault simulator; Acceleration; Circuit faults; Circuit simulation; Computational complexity; Computational modeling; Hardware; Integrated circuit modeling; Prototypes; Switches; Switching circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Rapid System Prototyping, 1993. Shortening the Path from Specification to Prototype. Proceedings., Fourth International Workshop on
Conference_Location :
Research Triangle Park, NC
Print_ISBN :
0-8186-4300-5
Type :
conf
DOI :
10.1109/IWRSP.1993.263191
Filename :
263191
Link To Document :
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