Variable ordering for regular layout representation

Author

Chrzanowska-Jeske, Malgorzata ; Xu, Yang

Author_Institution

Dept. of Electr. Eng., Portland State Univ., OR, USA

Volume

1

fYear

1998

fDate

1998

Firstpage

93

Abstract

We present new heuristics to minimize the size of recently developed new function representations, Pseudo-Symmetric Binary Decision Diagrams (PSBDDs). The PSBBD is a regular two-dimensional function representation which can be directly mapped to a layout with no placement or routing required. PSBDDs are especially useful for technologies where the circuit delay is limited by the delay of interconnects. A dynamic approach to the variable ordering problem was used to reduce the size of PSBDDs. Results for benchmark functions are very encouraging

Keywords

VLSI; binary decision diagrams; circuit layout CAD; integrated circuit layout; PSBBD; binary decision diagrams; circuit delay; heuristics; interconnect delay; pseudo-symmetric BDDs; regular 2D function representation; regular layout representation; variable ordering; Boolean functions; Data structures; Delay; Design methodology; Input variables; Integrated circuit interconnections; Optimization methods; Routing; Terminology; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1998 IEEE International Conference on

Conference_Location

Lisboa

Print_ISBN

0-7803-5008-1

Type

conf

DOI

10.1109/ICECS.1998.813278

Filename

813278