High performance interconnection architecture for large cellular neural networks

Several CNN hardware implementations have been presented in the last year. Most of them consist of one-chip circuits. Among the others, the authors presented the DPCNN chip family: a current-mode interconnection-oriented CNN analogue chip family. This approach presents many advantages and some drawbacks. In fact, simply connecting together more of these chips, it allows one to implement any size CNN arrays with the possibility to modify the network topology. On the other hand, it requires a high number of pads for the interconnections. Moreover, some parasitic capacitors due to the pads and the PCB wiring will appear. In this paper a high performance technique to improve the interconnection strategy able to overcome these drawbacks without any lack of functionality is presented