CMOS on-chip ESD protection design with substrate-triggering technique

To increase the ESD robustness and to reduce the trigger voltage of the ESD protection devices, a substrate-triggering technique is proposed to effectively enhance the ESD-protection efficiency of CMOS on-chip ESD protection circuits in submicron CMOS technologies. With suitable substrate bias, the ESD protection devices can sustain much higher ESD-stress voltage within small layout area. Two practical design examples of the input ESD protection circuit and the VDD-to-VSS ESD clamp circuit are designed by using the substrate-triggering technique to verify the ESD protection efficiency