50 MHz high-speed and 5 W low-power real-time programmable video multi processor (VMP) for MPEG-2 MP@ML on 0.6 μm TLM CMOS technology

Author

An, J.G. ; Shim, J.S. ; Kim, Y.M. ; Lee, M.M.-O.

Author_Institution

Dept. of Electron. Eng., Chonnam Nat. Univ., Kwangju, South Korea

Volume

1

fYear

1998

fDate

1998

Firstpage

463

Abstract

We developed a video multiprocessor (VMP) for image compression and decompression schemes of MPEG (especially MPEG-2) in this study. The VMP would apply to programmable architecture. Various flexibilities to implement real-time image compression algorithm, and many other applications such as DVD-CD ROM authoring tool and videophone/teleconferencing systems. I/O architecture of the VMP is designed for the multi processor functionality which uses many VMPs according to required arithmetic quantities of the system. Further, the architecture of the VMP system is simplified by processing the necessary peripheral I/O operations within the processor

Keywords

CMOS integrated circuits; data compression; digital signal processing chips; image coding; programmable circuits; real-time systems; teleconferencing; video signal processing; videotelephony; 0.6 micron; 5 W; 50 MHz; DVD-CD ROM authoring tool; MPEG-2 MP@ML; TLM CMOS technology; arithmetic quantities; image compression; image decompression; peripheral I/O operations; real-time programmable video multiprocessor; video multiprocessor; videophone/teleconferencing systems; Arithmetic; CMOS technology; Codecs; Image coding; Real time systems; Reduced instruction set computing; Signal processing algorithms; Streaming media; Transform coding; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1998 IEEE International Conference on

Conference_Location

Lisboa

Print_ISBN

0-7803-5008-1

Type

conf

DOI

10.1109/ICECS.1998.813363

Filename

813363