Title :
55-mW 1.2-V 12-bit 100-MSPS Pipeline ADCs for Wireless Receivers
Author :
Ito, Tomohiko ; Kurose, Daisuke ; Ueno, Takeshi ; Yamaji, Takafumi ; Itakura, Tetsuro
Author_Institution :
Corporate Res. & Dev. Center, Toshiba Corp., Kawasaki
Abstract :
For wireless receivers, low-power 1.2-V 12-bit 100-MSPS pipeline ADCs are fabricated in 90-nm CMOS technology. To achieve low-power dissipation at 1.2 V without the degradation of SNR, the configuration of 2.5bit/stage is employed with an I/Q amplifier sharing technique. Furthermore, single-stage common-source amplifiers are used in a sample-and-hold (S/H) circuit and a 1st multiplying digital-to-analog converter (MDAC). The common-source amplifier with two-stage transimpedance gain-boosting amplifiers realizes more than 90 dB. The measured SNR of the 100-MSPS ADC is 66.7 dB at 1.2-V supply. Under the condition, each ADC dissipates only 55 mW
Keywords :
CMOS integrated circuits; analogue-digital conversion; digital-analogue conversion; operational amplifiers; radio receivers; sample and hold circuits; 1.2 V; 12 bit; 55 mW; 90 nm; CMOS technology; I/Q amplifier sharing technique; S/H circuit; common-source amplifier; low-power dissipation; multiplying digital-to-analog converter; pipeline ADC; sample-and-hold circuit; single-stage common-source amplifiers; transimpedance gain-boosting amplifiers; wireless receivers; CMOS technology; Capacitors; Circuits; Degradation; Error correction; Operational amplifiers; Pipelines; Power amplifiers; Power dissipation; Sampling methods;
Conference_Titel :
Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European
Conference_Location :
Montreux
Print_ISBN :
1-4244-0303-0
DOI :
10.1109/ESSCIR.2006.307509
