DocumentCode :
3492758
Title :
A 100MHz hardware-efficient boost cascaded face detection design
Author :
Wong, Wei-Su ; Chen, Chih-Rung ; Chiu, Ching-Te
Author_Institution :
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear :
2009
fDate :
7-10 Nov. 2009
Firstpage :
3237
Lastpage :
3240
Abstract :
In this paper, we present a novel face detection architecture based on the boosted cascade algorithm. A reduced two-field feature extraction scheme for integral image calculation is proposed. Based on this scheme, the required memory for storing integral images is reduced from 400 Kbits to 2.016 Kbits for a 160×120 gray scale image. The range of the feature size and location is also reduced so the learning time of the classifier decreases around 10%. In addition, input data are mapped into parallel memories to enhance processing speed in classifier evaluations. This boosted cascade face detection hardware consumes only 0.992 mm2 under the UMC 90 nm technology and runs at 100 MHz. The experimental results show this face detector can achieve 91% face detection rate for processing 160×120 gray scale images at the speed of 190 fps.
Keywords :
computer aided instruction; face recognition; feature extraction; learning (artificial intelligence); boosted cascade algorithm; data mapping; face detection architecture; frequency 100 MHz; gray scale image; learning; parallel memories; two-field feature extraction scheme; Algorithm design and analysis; Computer architecture; Computer vision; Costs; Face detection; Feature extraction; Hardware; Humans; Image storage; Machine learning; AdaBoost; CMOS; Face detection; computer vision; machine learning;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Image Processing (ICIP), 2009 16th IEEE International Conference on
Conference_Location :
Cairo
ISSN :
1522-4880
Print_ISBN :
978-1-4244-5653-6
Electronic_ISBN :
1522-4880
Type :
conf
DOI :
10.1109/ICIP.2009.5414349
Filename :
5414349
Link To Document :
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