Title :
High tolerance to gate misalignment in graded channel double gate SOI n-MOSFETs: Small signal parameter analysis
Author :
Sharma, Rupendra Kumar ; Gupta, Mridula ; Gupta, R.S.
Author_Institution :
Dept. of Electron. Sci., Univ. of Delhi South Campus, New Delhi
Abstract :
Small signal parameter analysis for UD DG FD SOI n-MOSFET has been performed using ATLAS 3-D device simulator. It is found from the analysis that gate misalignment causes degradation in ac characteristics i.e. capacitance and cut-off frequency of the device. Using graded channel architecture i.e. high-low doping profile reduces/eliminate the effect of gate misalignment and thus improves the device performance.
Keywords :
MOSFET; silicon-on-insulator; ATLAS 3D device simulator; gate misalignment; graded channel architecture; graded channel double gate SOI; n-MOSFET; small signal parameter analysis; Analytical models; CMOS technology; Capacitance; Cutoff frequency; Doping profiles; MOSFET circuits; Signal analysis; Silicon on insulator technology; Sun; Threshold voltage;
Conference_Titel :
Microwave Conference, 2008. APMC 2008. Asia-Pacific
Conference_Location :
Macau
Print_ISBN :
978-1-4244-2641-6
Electronic_ISBN :
978-1-4244-2642-3
DOI :
10.1109/APMC.2008.4958636
