Impact of laterally asymmetric channel and gate stack design on device performance of surrounding gate MOSFETs : A modeling and simulation study

A two-dimensional analytical model is presented to study the impact of LACGAS device on the device characteristics. It is demonstrated that LACGAS leads to suppression of short channel effects such as threshold voltage (V_th) roll-off, drain induced barrier lowering (DIBL) and hot carrier effects. It also improves the transport efficiency owing to a greater gate control which is achieved by incorporating the stack architecture. Furthermore, LACGAS design also enables to obtain a high current drivability and enhancement in transconductance.