DocumentCode :
3492999
Title :
Architecture of a 100-Gbps network processor for next generation video networks
Author :
Koren, Guy ; Rosen, Amir
Author_Institution :
EZchip Technol., Israel
fYear :
2010
fDate :
17-20 Nov. 2010
Abstract :
As the escalating demand for bandwidth continues, 100-Gigabit networks mark the new frontier to be ventured by networking equipment vendors. Network processors (NPUs), fast emerging as key components in 10-Gigabit platforms, will also empower the 100-Gigabit platforms. However, packet processing at these line rates presents significant challenges to network processor designs. The most important driving factor for the exploding bandwidth demand is video traffic. Supporting video traffic imposes even further challenges due to its real time and low jitter requirements. These challenges are amplified when attempting to construct a network with IPTV-grade capabilities. In order to address these challenges it is crucial for the routers, and the network processors in their cores, to be video aware and demonstrate special treatment for this demanding traffic.
Keywords :
IPTV; jitter; multiprocessing systems; next generation networks; telecommunication network routing; telecommunication traffic; video communication; 100-gigabit networks; IPTV-grade capability; bit rate 100 Gbit/s; driving factor; jitter; network processor designs; networking equipment vendors; next generation video networks; packet processing; video traffic; Bandwidth; Hardware; IP networks; Protocols; Quality of service; Streaming media; Transform coding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical and Electronics Engineers in Israel (IEEEI), 2010 IEEE 26th Convention of
Conference_Location :
Eliat
Print_ISBN :
978-1-4244-8681-6
Type :
conf
DOI :
10.1109/EEEI.2010.5661977
Filename :
5661977
Link To Document :
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