Implementation of photo-imagers in a 0.8 μm double-polysilicon bipolar process

Author

Rowley, Matthew D. ; Lim, Shao-Jen ; Harris, John G. ; O, Kenneth K.

fYear

1997

fDate

28-30 Sep 1997

Firstpage

116

Lastpage

119

Abstract

High-speed, low-power image processing can be performed by architectures incorporating onchip, near-sensor processing in high-speed bipolar processes. To date, most imaging architectures have been implemented in CMOS or CCD processes. This paper discusses characteristics of 1-D imagers fabricated in a 0.8 μm double-polysilicon bipolar process for use in integrated remote imager applications with wireless links. The imager consists of continuous-time logarithmic photodetectors coupled to Darlington buffers

Keywords

analogue processing circuits; bipolar analogue integrated circuits; image sensors; photodetectors; 0.8 micron; 1D imagers; Darlington buffers; continuous-time logarithmic photodetectors; double-polysilicon bipolar process; high-speed bipolar processes; imaging architecture; low-power image processing; near-sensor processing; photo-imagers; wireless links; Automatic control; CMOS process; CMOS technology; Charge coupled devices; Circuits; Detectors; Image processing; Motion control; Photodetectors; Robot control; Shift registers; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting, 1997. Proceedings of the

Conference_Location

Minneapolis, MN

ISSN

1088-9299

Print_ISBN

0-7803-3916-9

Type

conf

DOI

10.1109/BIPOL.1997.647413

Filename

647413