A high power density 26 V GaAs pHEMT technology

This report presents a GaAs pHEMT technology optimized for 26 V drain bias. At this bias, a 2.14 GHz gate width scaling study demonstrates output power densities of 1.8-2.1 W/mm of output power at 1 dB gain compression (P_1dB) for device sizes ranging from 14.4 mm down to 3.6 mm respectively. Power added efficiency (PAE) remains nearly constant at 59-61% for these device sizes. Devices with 14.4 mm gate widths produced a Pias of 26 W (1.8 W/mm) with an associated power-added efficiency (PAE) of 61%. Thermal imaging shows a thermal resistance of approximately 4.2°C/W at a 36°C case temperature for 14.4 mm (26 W) devices. A high temperature step stress reliability study shows a median time to failure (MTTF) of 1.6×10⁷ hours for a 150°C channel temperature with a thermal activation energy of 1.8 eV. These results represent the best combination of power density, PAE, and reliability reported for any GaAs-based FET technology.