Design and analysis of a new sub-threshold DTMOS SRAM cell structure

In this paper, we propose a novel dynamic threshold (DTMOS) based fully differential ten-transistor (10T) SRAM (Static Random Access Memory) cell suitable for sub-threshold operation. The structure has two inverters in addition to the conventional 6T standard cell. It provides better read current, increased read and hold static noise margins (SNM) and improved write time compared to a recently proposed sub-threshold SRAM cell. The stability of sub-threshold DTMOS SRAM to process variations is also investigated. The robust dynamic threshold based memory cell exhibits built-in process variation tolerance that gives tight SNM distribution across the process corners.