DocumentCode
3495175
Title
A Reconfigurable Simulation Framework for Financial Computation
Author
Bower, Jacob A. ; Thomas, David B. ; Luk, Wayne ; Mencer, Oskar
Author_Institution
Dept. of Comput., Imperial Coll., London
fYear
2006
fDate
Sept. 2006
Firstpage
1
Lastpage
9
Abstract
This paper presents a framework for the acceleration of Monte-Carlo simulations using reconfigurable hardware. Discrete-time random walk simulations are widely used in the financial computation to calculate derivative prices and evaluate portfolio risk, but increases in model complexity and tighter time constraints now require large computer farms to meet operational demands. We present a model for accelerating such tasks with reconfigurable hardware, using an architecture that exploits parallelism at multiple levels, combining fine-grained pipelining, intra-device multi-threading and inter-device distributed processing. The architecture adopts a modular design approach, allowing components to be re-used across different applications, while also allowing automatic design space exploration to maximise performance within different devices. Using our framework, we implement two different discrete-time random walks representative of financial simulations and these show 71 times and 8 times speedup respectively when compared to a C++ software and SSE vectorised implementations
Keywords
Monte Carlo methods; field programmable gate arrays; financial data processing; multi-threading; object-oriented programming; software reusability; Monte-Carlo simulation; automatic design space exploration; component reusability; discrete-time random walk simulation; financial computation; fine-grained pipelining; inter-device distributed processing; intra-device multithreading; reconfigurable hardware; Acceleration; Computational modeling; Computer architecture; Computer simulation; Distributed processing; Hardware; Parallel processing; Pipeline processing; Portfolios; Time factors;
fLanguage
English
Publisher
ieee
Conference_Titel
Reconfigurable Computing and FPGA's, 2006. ReConFig 2006. IEEE International Conference on
Conference_Location
San Luis Potosi
Print_ISBN
1-4244-0690-0
Electronic_ISBN
1-4244-0690-0
Type
conf
DOI
10.1109/RECONF.2006.307750
Filename
4099970
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