Speculative completion for the design of high-performance asynchronous dynamic adders

Author

Nowick, Steven M. ; Yun, K.Y. ; Beerel, Peter A. ; Dooply, Ayoob E.

Author_Institution

Dept. of Comput. Sci., Columbia Univ., New York, NY, USA

fYear

1997

fDate

7-10 Apr 1997

Firstpage

210

Lastpage

223

Abstract

This paper presents an in-depth case study in high-performance asynchronous adder design. A recent method, called “speculative completion”, is used. This method uses single-rail bundled datapaths but also allows early completion. Five new dynamic designs are presented for Brent-Kung and Carry-Bypass adders. Furthermore, two new architectures are introduced, which target (i) small number addition, and (ii) hybrid operation. Initial SPICE simulation and statistical analysis show performance improvements up to 19% on random inputs and 14% on actual programs for 32-bit adders, and up to 29% on random inputs for 64-bit adders, over comparable synchronous designs

Keywords

SPICE; adders; asynchronous circuits; logic CAD; SPICE simulation; adders; asynchronous; asynchronous dynamic adders; high-performance; performance improvements; single-rail bundled datapaths; speculative completion; Analytical models; Clocks; Delay; Distributed computing; Engineering profession; SPICE; Scalability; Statistical analysis; Synchronization; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Research in Asynchronous Circuits and Systems, 1997. Proceedings., Third International Symposium on

Conference_Location

Eindhoven

Print_ISBN

0-8186-7922-0

Type

conf

DOI

10.1109/ASYNC.1997.587176

Filename

587176