A simulator-optimizer for the design of very low phase noise CMOS LC-oscillators

Author

De Muer, B. ; De Ranter, C. ; Crols, J. ; Steyaert, M.

Author_Institution

ESAT, Katholieke Univ., Leuven, Heverlee, Belgium

Volume

3

fYear

1999

fDate

1999

Firstpage

1557

Abstract

A simulator-optimizer program for spiral inductors on silicon substrates is presented. The program implements the three-dimensional inductance extraction program FastHenry in a simulated annealing optimization loop. The simulated annealing algorithm performs the optimization of automatically generated spiral inductor geometries towards an optimal quality factor for a specified technology. Using the program, a low-phase-noise LC-tank Voltage Controlled Oscillator (VCO) is integrated in a 0.65 μm BiCMOS process. The phase noise is as low as -127.5 dBc/Hz at an offset frequency of 600 kHz from a 1.33 GHz carrier, while consuming only 10 mA from a 2 V power supply

Keywords

CMOS analogue integrated circuits; Q-factor; UHF integrated circuits; UHF oscillators; circuit CAD; circuit optimisation; circuit simulation; inductors; integrated circuit design; integrated circuit noise; phase noise; silicon; simulated annealing; voltage-controlled oscillators; 0.65 micron; 1.33 GHz; 10 mA; 2 V; 3D inductance extraction program; CMOS LC oscillators; FastHenry; LC-tank VCO; Si; Si substrates; optimal quality factor; simulated annealing optimization loop; simulator-optimizer program; spiral inductors; submicron BiCMOS process; very low phase noise oscillators; voltage controlled oscillator; Geometry; Inductance; Inductors; Phase noise; Q factor; Silicon; Simulated annealing; Solid modeling; Spirals; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on

Conference_Location

Pafos

Print_ISBN

0-7803-5682-9

Type

conf

DOI

10.1109/ICECS.1999.814468

Filename

814468