• DocumentCode
    349732
  • Title

    A new general connectivity model and its applications to timing-driven Steiner tree routing

  • Author

    Wang, Dongsheng ; Kuh, Ernest S.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
  • Volume
    2
  • fYear
    1998
  • fDate
    1998
  • Firstpage
    71
  • Abstract
    In this paper, we first construct a general connectivity graph from a given net based on some pertinent observations of the Elmore delay model. The graph is defined as a weighted directed connection graph (DCG) which is used to describe the “edge connectivity” of all the edges on the graph. Then a timing-driven Steiner tree routing approach, called the C-Tree algorithm, is proposed. It constructs an initial spanning tree by the method of edge elimination on graph DCG. Next, the initial tree is improved to achieve a better area/delay trade-off by maximizing “path connectivity” of the minimum connectivity path (MCP). Finally, the spanning tree is transformed to the corresponding Steiner tree. Experiments show that the C-Tree algorithm is promising
  • Keywords
    circuit layout CAD; delays; directed graphs; edge detection; integrated circuit layout; network routing; timing; trees (mathematics); C-Tree algorithm; Elmore delay model; area/delay trade-off; edge connectivity; edge elimination; general connectivity model; minimum connectivity path; path connectivity; timing-driven Steiner tree routing; weighted directed connection graph; Application software; Costs; Delay effects; Minimization methods; Routing; Steiner trees; Timing; Tree data structures; Tree graphs; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems, 1998 IEEE International Conference on
  • Conference_Location
    Lisboa
  • Print_ISBN
    0-7803-5008-1
  • Type

    conf

  • DOI
    10.1109/ICECS.1998.814828
  • Filename
    814828