Architecture of a coprocessor module for image compositing

This paper proposes the architecture of a coprocesssor module for image compositing. The emerging MPEG-4 standard for multimedia applications allows script-based compositing of audiovisual scenes from multiple audio and visual objects. This involves the composition of the output frame by alpha-blending of Video Object Planes (VOPs). A coprocessor architecture is presented, that works in parallel to an MPEG-4 video- and audio-decoder, and performs computation and bandwidth intensive low-level algorithms for image compositing. The processor has on-chip memories that allow preload of data before it is accessed. VHDL implementation and synthesis for a 0.5μ process show an estimate of 100 MHz achievable clock-frequency and 10 k gates for arithmetic and control circuitry which results in roughly 5 mm² silicon area. Overall performance is sufficient to compose more than 5 full-screen VOPs with a background of size 704×576 each at 30 Hz