A double-edge implicit-pulsed level convert flip-flop

Clustered voltage scaling (CVS) systems is a technique to decrease power dissipation. One of the design challenges in CVS is the efficient level converter with fewer overheads in power and delay. In this paper, we propose a novel implicit-pulsed level convert flip-flop that uses circuit techniques such as conditional discharge to reduce the overhead incurred with level conversion flip-flops (LCFF). Double-edge triggering is also used to further decrease the power consumption. In view of power, the new LCFF outperform previous published designs about 18%-56% and exhibit smaller delay and PDP.