High-speed/high-density logic circuit design

Problems and possible solutions to implement high-speed logic VLSI´s with advanced CMOS/BiCMOS technology are discussed. The technology trend is summarized first in conjunction with its impact on the circuit designs. The paper covers BiCMOS circuit designs and other basic high-speed circuit techniques including gate sizing, dynamic/reduced swing circuits, interconnect/clock delay, and on-chip memory. These items are discussed with possible scaling effects. Future high-speed design should cope with low-V_DD related problems including threshold voltage scaling, interconnection delay problems including clock distribution problems, power and noise.