Enhancement of the Illinois scan architecture for use with multiple scan inputs

Testing cost is becoming increasingly important as system-on-chip circuits continue to become more complex. In this paper, we address the issue of reducing test cost by shortening test application time and reducing the volume of data needs to be stored on a tester. The number of scan channels on a tester and/or the number of pins on an SOC are limited. We propose a method to enhance the Illinois scan architecture for use with a small number of scan-in pins. Pin reduction is achieved by connecting a single pin to several scan chains together depending on their compatibility relations. With the use of an incompatibility graph and graph colouring algorithm, the number of pins needed is minimized.