Title :
Optimization methods of delay and chip area in designing high speed VLSI modules
Author :
Asada, Kunihiro ; Fujishima, Minoru ; Ikeda, Makoto ; Zhang, Hongming
Author_Institution :
Dept. of Electron. Eng., Tokyo Univ., Japan
Abstract :
Design methods of speed-area optimization for high speed VLSI logic modules are presented, from view points of (1) area optimization under timing constraints, (2) speed optimum circuits free from area constraints and (3) low cost strategies for high speed signal transmission on chip. After introducing concepts and underlying theories, several examples of optimum design are presented.
Keywords :
VLSI; logic CAD; modules; optimisation; algorithm; high speed VLSI modules; high speed signal transmission on chip; logic modules; low cost strategies; multistage complex gate circuits; optimization methods; speed optimum circuits; speed-area optimization; timing constraints; two-step transistor sizing method; Constraint optimization; Cost function; Delay; Design methodology; Design optimization; Logic circuits; Logic design; Optimization methods; Timing; Very large scale integration;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on
Conference_Location :
Taipei, Taiwan
Print_ISBN :
0-7803-0978-2
DOI :
10.1109/VTSA.1993.263623
