DocumentCode :
3498624
Title :
Boolean matching algorithms
Author :
Chen, Kuang-Chien ; Yang, Jerry Chih-Yuan
Author_Institution :
Fujitsu America Inc., San Jose, CA, USA
fYear :
1993
fDate :
1993
Firstpage :
44
Lastpage :
48
Abstract :
The authors consider the problem of detecting the equivalence of two single-output Boolean functions, considering the permutation and complementation of their inputs, complementation of outputs, and associated don´t-care sets, which is often referred to as the Boolean matching problem. Boolean matching is a verification problem, and it has important applications in logic synthesis problems such as technology-mapping. Several new approaches are presented for solving the Boolean matching problem. The features and efficiency of these algorithms are discussed. The author also compare with an existing Boolean matching algorithm by applying them to the technology-mapping of cell based designs.
Keywords :
Boolean functions; formal verification; logic design; Boolean matching algorithms; cell based designs; complementation; don´t-care sets; equivalence; inputs; logic synthesis; outputs; permutation; single-output Boolean functions; technology-mapping; verification problem; Algorithm design and analysis; Boolean functions; Libraries; Logic design; Smoothing methods; Terminology; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on
Conference_Location :
Taipei, Taiwan
ISSN :
1524-766X
Print_ISBN :
0-7803-0978-2
Type :
conf
DOI :
10.1109/VTSA.1993.263624
Filename :
263624
Link To Document :
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