On the reduction of simultaneous switching in SoCs

The inexorable scaling of technology into the deep submicron era has been fuelled by the requirements of high performance, high on-chip integration of complex logic blocks, and short time-to-market windows. This has ensured that today´s designs are densely packed systems of IP-cores, integrated on single chips. This leads to simultaneous switching noise (SSN) in the power and ground networks, which can be large enough to cause both functional and timing failures in the circuits. We propose a systematic approach to integrate clock tuning and flip-flop insertion to optimally spread out the switching times of IP-cores in system-on-s-chip circuits. A relaxation based method has been used to efficiently solve the above problem, and our experiments on wireless transceiver circuits show that we achieve a 30% reduction, on average, of maximum simultaneous switching current over the unoptimized circuits.