Title :
Abstract system-level models for early performance and power exploration
Author :
Gerstlauer, Andreas ; Chakravarty, Suhas ; Kathuria, Manan ; Razaghi, Parisa
Author_Institution :
Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA
fDate :
Jan. 30 2012-Feb. 2 2012
Abstract :
With increasing complexity of today´s embedded systems, research has focused on developing fast, yet accurate high-level and executable models of complete platforms. These models address the need for hardware/software co-simulation of the entire system at early stages of the design. Traditional models tend to be either slow or inaccurate. In this paper, we present ingredients for a class of abstract, high-level platform models that enable fast yet accurate performance and power simulation of application execution on heterogeneous multi-core/-processor architectures. Models are based on host-compiled simulation of the application code, which is instrumented with timing and power information. Back-annotated source code is further augmented with abstract OS and processor models that are integrated into standard co-simulation backplanes. The efficiency of the modeling platform has been evaluated by applying an industrial-strength benchmark, demonstrating the feasibility and benefits of such models for rapid, early exploration of the power, performance and cost design space. Results show that an accurate Pareto set of solutions can be obtained in a fraction of the time needed with traditional simulation and modeling approaches.
Keywords :
embedded systems; hardware-software codesign; multiprocessing systems; Pareto set; abstract OS; abstract system-level model; application code; application execution; back-annotated source code; co-simulation backplane; cost design space; embedded system; hardware-software co-simulation; heterogeneous multicore architecture; heterogeneous multiprocessor architecture; high-level platform model; host-compiled simulation; industrial-strength benchmark; power exploration; power simulation; Accuracy; Computational modeling; Kernel; Multicore processing; Time domain analysis; Time varying systems; Timing;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific
Conference_Location :
Sydney, NSW
Print_ISBN :
978-1-4673-0770-3
DOI :
10.1109/ASPDAC.2012.6164947